1. Field of the Invention
The present invention relates to semiconductor device manufacture. More particularly this invention relates to transistor gate electrode materials.
2. Discussion of Related Art
During the past two decades, the physical dimensions of MOSFETs have been aggressively scaled for low-power, high-performance CMOS applications. In order to continue scaling future generations of CMOS, the use of metal gate electrode technology is important. For example, further gate insulator scaling will require the use of dielectric materials with a higher dielectric constant than silicon dioxide. Devices utilizing such gate insulator materials demonstrate vastly better performance when paired with metal gate electrodes rather than traditional poly-silicon gate electrodes.
Depending on the design of the transistors used in the CMOS process, the constraints placed on the metal gate material are somewhat different. For a planar, bulk or partially depleted, single-gate transistor, short-channel effects (SCE) are typically controlled through channel dopant engineering. Requirements on the transistor threshold voltages (V1) then dictate the gate work-function values must be close to the conduction and valence bands of the substrate semiconductor. A “mid-gap” work function gate electrode that is located too close to the middle of the p and n channel work function range is inadequate because it typically results in a transistor having either a threshold voltage that is too large for high-performance applications or a compromised SCE when the effective channel doping is reduced to lower the threshold voltage. For non-planar or multi-gate transistor designs, the device geometry better controls SCE and the channel may then be more lightly doped and potentially fully depleted at zero gate bias. For such devices, the threshold voltage can be determined primarily by the gate metal work function. However, even with the multi-gate transistor's improved SCE, it is typically necessary to have a gate electrode work function about 250 mV above mid-gap for an nMOS transistor and about 250 mV below mid-gap for a pMOS transistor. Therefore, a single mid-gap gate material is also incapable of achieving ideal threshold voltages for both pMOS (a MOSFET with a p-channel) and nMOS (a MOSFET with an n-channel) multi-gate transistors.
For these reasons, CMOS devices generally utilize two different metal gate electrodes, an n-type electrode and a p-type electrode, having two different work function values. A gate electrode has an n-type work function if the electrode material's work function is near (e.g., within +/−0.3 eV) of the energy level of the underlying substrate material's conduction band. Conversely, a gate electrode has a p-type work function if the electrode material's work function is near the energy level of the substrate material's valence band. Silicon has a conduction band energy level of approximately 4.1 eV and a valence band energy level of approximately 5.2 eV. Thus, for a silicon substrate, the gate electrode of a negative channel MOSFET (or NMOS) device would have an n-type work function of approximately 4.1 eV (+/−0.3 eV), and the gate electrode of a positive channel MOSFET (or PMOS) device would have a p-type work function of approximately 5.2 eV (+/−0.3 eV). To change the work function of metal gate materials and achieve desired threshold voltages, two different metals are typically utilized for nMOS and pMOS devices. This method is commonly referred to a dual-metal gate CMOS process.
The n-type and p-type metal gate materials used to set work function may not be good conductors. In this case, it is desirable to use a relatively thin layer of the work function metal having optimal work function characteristics to achieve a desired threshold voltage, and then form another layer of a relatively good conductor over the work function metal to keep the gate electrode resistance low while keeping the work function metal thickness to a minimum so that manufacturing is simplified. For example, a silicided polysilicon capping layer may be formed over the work function metal to lower the bulk resistance of the gate electrode. One such conventional CMOS device 100 is shown in FIG. 1, where substrate 105, has a pMOS device with a p-channel 115 and an nMOS device with an n-channel 120. The pMOS device 115 having a source and drain 110 proximate to a gate isolation spacer 108 surrounding a gate stack. The gate stack including a gate insulator 140 and a gate electrode having a p-metal 160 (a metal having a work function appropriate for a low pMOS transistor threshold voltage) and silicided polysilicon cap 180. The nMOS device 120 having a source and drain 111 proximate to a gate isolation spacer 108 surrounding a gate stack. The gate stack including the gate insulator 140 and a gate electrode having an “n-metal” 150 (a metal having a work function appropriate for a low nMOS transistor threshold voltage), the “p-metal” 160, and silicided polysilicon cap 180. The p-metal 160 may be tolerated as an artifact in the nMOS device gate stack in favor of reducing the number of masking steps required to define the gate stacks of the CMOS device.
However, even with silicided polysilicon cap 180, the bulk resistance of the gate electrode, becomes unacceptably high as the dimension of the gate electrode is scaled. While a low resistance metal, such as aluminum, could be employed to further lower the gate electrode bulk resistance below that achievable with silicided polysilicon cap 180, the presence of a low resistance capping metal in close proximately to the MOS junction is problematic for many reasons. Most notably, diffusion of the capping metal into the MOS junction can cause deep level traps shifting threshold voltages or otherwise render a transistor inoperable.